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DVB-S2 Modulator IP Core
The DVB-S2 Modulator IP Core implements a DVB-S2 compliant modulator. The core accepts an input stream of MPEG2 TS-packets over an ASI interface, and after performing all necessary BB, FEC and PL processing, provides a stream of complex-valued samples which are pushed to the HDRM-M modulator block (included) for sample-rate conversion and RRC filtering.
Functional blocks include:
•MPEG2 TS alignment recovery and buffering
•Baseband (BB) frame construction
•BCH and LDPC FEC processing
•Physical Layer (PL) frame construction
The DVB-S2 Modulator IP Core processes a single MPEG2 TS-packet stream and drives a complex baseband output signal to the HDRM-M Modulator core (included). Incoming TS-packets are buffered in a 16K-byte ASI input FIFO before being consumed by the internal processing blocks. A FIFO level signal is available so that external circuitry can control the flow of packets into the core. If the FIFO does not contain enough information to allow a BB frame to be constructed the core will send dummy PL frames until ready.
The DVB-S2 Modulator instantiates the Xilinx DVB-S2 FEC Encoder LogiCORE. Users of the DVBS2-M modulator core must acquire a licence to this Xilinx core in order to generate a usable design.
Functional blocks include:
•MPEG2 TS alignment recovery and buffering
•Baseband (BB) frame construction
•BCH and LDPC FEC processing
•Physical Layer (PL) frame construction
The DVB-S2 Modulator IP Core processes a single MPEG2 TS-packet stream and drives a complex baseband output signal to the HDRM-M Modulator core (included). Incoming TS-packets are buffered in a 16K-byte ASI input FIFO before being consumed by the internal processing blocks. A FIFO level signal is available so that external circuitry can control the flow of packets into the core. If the FIFO does not contain enough information to allow a BB frame to be constructed the core will send dummy PL frames until ready.
The DVB-S2 Modulator instantiates the Xilinx DVB-S2 FEC Encoder LogiCORE. Users of the DVBS2-M modulator core must acquire a licence to this Xilinx core in order to generate a usable design.
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