DMA AXI4-Stream to/from AXI4 Memory Map - Scatter-Gather Descriptor List
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Dual WideBand Frequency Synthesizer with Integrated VCO and Loop Filter
CorePLL is a wideband phase-locked loop (PLL) system for 2G (GSM) 3G and 4G (LTE), including Carrier Aggregation (CA) for 3GPP Rel11 and Rel12. CorePLL frequency synthesis sub-system enables single transceiver LTE CA. CorePLL consists of two fully integrated PLLs with integrated VCOs and loop filters. CorePLL is versatile frequency synthesizer solution with small size, high-performance and ultra low-power. Power consumption is only 18mA from 1.35V supply (24mW). CorePLL supports variety of different systems and reference clock frequencies. CorePLL is implemented using standard 55nm CMOS process. CorePLL is available in QFN 6x6mm package. PLL1 and PLL2 synthesizers are also available as IPs.
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Block Diagram of the Dual WideBand Frequency Synthesizer with Integrated VCO and Loop Filter
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