MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, N7, N5A)
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Dual Port SRAM Compiler IP, UMC 0.11um HS/FSG process
UMC 0.11um HS/RVT Logic process synchronous high density Dual Port SRAM memory compiler.
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