MIPI D-PHY Universal IP - 4.5Gbps/lane, MIPI D-PHY v2.5 Compliant in TSMC 22ULP
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Dual Port SRAM Compiler IP, Support Repair Features, UMC 55nm SP process
UMC 55nm 1.0V Standard Performance (SP) Low-K Logic process synchronous, high density, Dual Port SRAM with row redundancy option.
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