MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, N7, N5A)
Dual Channel Digital Capacitive Sensor Interface
needed.
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Capacitance IP
- Analog I/O - low capacitance, low leakage
- Hyper-Decoupling Capacitor with a Capacitance Multiplication, Series Inductance Nullification, Cybersecurity Enhancement and an Energy Harvesting capabilities
- RF ESD specifiically targeting low capacitance ESD
- Digital Capacitive Sensor Interface
- Digital Capacitive Plus Bridge Sensor Interfaces
- 8-Channel Ultra-Low Power Capacitive Touch Interface