You are here:
Dual 80MSPS 10 bit ADC for IQ
Dual channel ADC for Wireless applications
特色
- 65nm 6 Metal CMOS (No analog options)
- 3V power supply
- 1 Vpp differential input range
- Dual 80MSPS operation
- Dynamic performance
- 56dB SINAD at fIN=20MHz
- 68dB SFDR at fIN=20MHz
- DNL 0.5 LSB
- INL 1 LSB
- Total Die area of 1mm2
- Power/sample rate scalability
- 71mW at 80 MSPS
- 40mW at 40 MSPS
- Stand-by and power down modes
- Analog test input signal port
- Scan test for digital section
优势
- This ADC has been designed to reduce time to market, risk and cost in the development of analog front-ends. This dual channel ADC accepts an 80MHz input clock to operate at 80Ms/s per channel. It uses the 2 ADC cores with shared references and timing to ensure excellent matching performance.
- The ADC has a pipeline architecture with differential input in order to maximize dynamic range and noise immunity. Digital correction of the 9 MSB bits ensures good linearity approaching Nyquist.
可交付内容
- Datasheet
- Characterization Report
- Flat Netlist (cdl)
- Layout View (gds2)
- Abstract View (lef)
- Timing View (tlf)
- Behavioral Model (VHDL/Verilog)
- Silicon Samples
- DemonstrationEvaluation Board
- Integration Support
查看 Dual 80MSPS 10 bit ADC for IQ 详细介绍：
- 查看 Dual 80MSPS 10 bit ADC for IQ 完整数据手册
- 联系 Dual 80MSPS 10 bit ADC for IQ 供应商