This IP macro contains dual 11- bit 650 MHz analog-to-digital converters (ADC) designed using the TSMC 65nm LP process. Each ADC uses a successive approximation register (SAR) architecture. The dual 11-bit ADC is powered from a 2.5V analog, a 1.2V analog, and a 1.2V digital supply. The ADC is designed to receive a differential Current Mode Logic (CML) clock and outputs 11 bits in a two€™s complement format. The ADC also supplies an output clock which can be used to clock the data into registers in the core logic circuitry.