UCIe/BoW BlueLynx™ Dual Mode PHY and subsystem IP for chiplet interconnect
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DSC 1.2b Encoder
The DSC 1.2b Encoder is an efficient video compression IP that complies with the VESA Display Stream Compression (DSC) 1.2b standard. Optimized for low power consumption and compact size, this IP delivers real-time, visually lssless video encoding for high-bandwidth display applications. It is compatible with several transport standards, including MIPI DSI-2 1.1, DisplayPort 1.4, and HDMI 2.1. The encoder supports all DSC 1.2b coding schemes, such as MMAP, BP, MPP, and ICH, and handles multiple color formats including YCbCr 4:4:4, 4:2:2, 4:2:0, and RGB. Additionally, the core is cost-effective and scalable, meeting the demands of higher resolution or higher frame rate displays, and supports up to 2-slice encoding.
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Block Diagram of the DSC 1.2b Encoder
DSC IP
- VESA DSC (Display Stream Compression) 1.2b Video Encoder
- VESA DSC (Display Stream Compression) 1.2b Video Decoder
- ASIL-B Ready ISO 26262 Certified VESA DSC (Display Stream Compression) 1.1 Encoder
- VESA DisplayPort 1.4 RX IP Subsystem for Xilinx FPGAs
- VESA DSC 1.2b Encoder for Xilinx FPGAs
- VESA DSC 1.2b Decoder IP Core for Xilinx FPGAs