The Xilinx® Deep Learning Processor Unit (DPU) is a programmable engine dedicated for convolutional neural network. The unit contains register configure module, data controller module, and convolution computing module. There is a specialized instruction set for DPU, which enables DPU to work efficiently for many convolutional neural networks. The deployed convolutional neural network in DPU includes VGG, ResNet, GoogLeNet, YOLO, SSD, MobileNet, FPN, etc.
The DPU IP can be integrated as a block in the programmable logic (PL) of the selected Zynq®-7000 SoC and Zynq UltraScale™+ MPSoC devices with direct connections to the processing system (PS). To use DPU, you should prepare the instructions and input image data in the specific memory address that DPU can access. The DPU operation also requires the application processing unit (APU) to service interrupts to coordinate data transfer.
- One slave AXI interface for accessing configuration and status registers
- One master interface for accessing instructions
- Supports configurable AXI master interface with 64 or 128 bits for accessing data
- Supports individual configuration of each channel
- Supports optional interrupt request generation
- Some highlights of DPU functionality include:
- Configurable hardware architecture includes: B512, B800, B1024, B1152, B1600, B2304, B3136, and B4096
- Configurable core number up to three
- Convolution and deconvolution
- Max pooling
- ReLu and Leaky ReLu
- Fully connected layer
- Batch Normalization