MIPI D-PHY Universal IP - 4.5Gbps/lane, MIPI D-PHY v2.5 Compliant in TSMC 22ULP
DPI video output to system memory capture IP block
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Display Output IP
- VESA DSC (Display Stream Compression) 1.2b Video Encoder
- VESA DSC (Display Stream Compression) 1.2b Video Decoder
- VDC-M (VESA Display Compression-M) Decoder
- One Input to One Output MIPI DSI Display Interface Bridge
- One Input to Two Output MIPI DSI Display Splitter Bridge
- Customizable Display Controller with composition support