DPA- and FIA-Resistant Balanced FortiCrypt AES IP Core

Intro
The AES SX-DPA-FIA IP Core is a part of the FortiCrypt product family. It provides a balanced solution with a gate count comparable to unprotected solutions and the same latency and performance as unprotected solutions have, thereby upholding the original AES design goals of high performance, low latency, and gate count.

This is a unique solution in the market since it combines protection against SCA and FIA with the same latency and performance as, and a gate count comparable to unprotected implementations.

The AES SX-DPA-FIA IP Core, as well as all the FortiCrypt products, is based on RAMBAM - the next-generation purely algorithmic, implementation-agnostic protection scheme of AES. It is designed to provide the highest level of protection against side-channel attacks (SCA) and fault injection attacks (FIA) including SIFA.

The RAMBAM protection scheme utilizes masking methods based on finite field arithmetic that implement attack resistance without incurring extra latency costs.

The core protection mechanism was verified using the rigorous Test Vector Leakage Assessment (TVLA) test at 1B traces, both by FortifyIQ and by a third-party Common Criteria lab. Resistance to attacks was validated analytically and on a physical device. The cores are fully synthesizable and do not require custom cells or special place & route handling.

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