The Soft Error Mitigation (SEM) IP core performs SEU detection, correction, and classification. The core utilizes device primitives such as Virtex™-7 ICAP and ECC blocks to clock and observe the readback CRC circuit as part of the SEU detection function. For SEU correction, the IP core performs the necessary operations to locate and correct SEU errors using the Virtex™-6 built-in ECC facility. For SEU classification, the IP core uses Xilinx Essential Bits technology to further increase system reliability.
The SEM IP core also performs emulation of SEUs within 7-Series, Virtex™-6 and Spartan®-6 devices by injecting errors into the configuration memory. The error injection feature provides a means to evaluate and test the readback CRC circuit and the error correction capabilities of the IP core which is impossible with real SEUs.