Provides a point-to-point bi-directional interface between a user IP core and the AXI interconnect, optimized for slave operation on the AXI. It does not provide support for DMA and IP Master Services. Basically it is a simple (slower) interface for user logic to connect to AXI bus to communicate with the microprocessor.
- Supports 32-bit slave configuration
- Supports read and write data transfers of 32-bit width
- Supports multiple address ranges
- If there is a simultaneous read/write on AXI, read has the higher priority over write
- Reads to the holes in the address space returns 0×00000000
- Writes to the holes in the address space after the register map are ignored and responded with an OKAY response.
- IPIF will not perform endian conversion. Both AXI and IP Interconnect (IPIC) are little endian.
- Mature source IP has been re-engineered for full DAL-A compliance for airworthiness and design assurance for safety-critical programs, supporting and simplifying the compliance effort at the FPGA level.
- Encrypted source along with a complete certification data package (CDP) including all artifacts required for chip-level compliance.