Connects through an AXI4-Lite interface and provides the controller interface for asynchronous serial data transfer.
- AXI interface is based on AXI4-Lite specification
- Hardware and software register compatible with all standard 16450 and 16550 UARTs
- Supports default core configuration for 9600 baud, 8 bits data length, 1 stop bit and no parity
- Implements all standard serial interface protocols
- Mature source IP has been re-engineered for full DAL-A compliance for airworthiness and design assurance for safety-critical programs, supporting and simplifying the compliance effort at the FPGA level.
- Encrypted source along with a complete certification data package (CDP) including all artifacts required for chip-level compliance.