The core provides a point to point bi-directional interface between a user IP core and the AXI4 interconnect (to provide a smooth migration path to the burst-supported IP from PLBv46 to AXI4 with minor updates in the interface. ). This core acts as master on IPIC while it behaves as a slave on AXI4.
- AXI4 Interface: 32 Bit Address bus, 32/64/128 Bit configurable data bus
- IPIC Interface: 32 Bit Address bus, 32/64/128 Bit configurable data bus
- Supports 1:1 (AXI4:IPIC) synchronous clock
- Supports 1:1 (AXI4:IPIC) data width
- AXI4 Interface
- IPIC Interface
- Mature source IP has been re-engineered for full DAL-A compliance for airworthiness and design assurance for safety-critical programs, supporting and simplifying the compliance effort at the FPGA level.
- Encrypted source along with a complete certification data package (CDP) including all artifacts required for chip-level compliance.