Provides a serial interface to SPI devices such as SPI EEPROMs and SPI serial flash devices. Not needed for Zynq unless >2 needed. Connects
- AXI4-Lite interface is based on the AXI4 specification
- Connects as a 32-bit AXI4-Lite slave
- Supports four signal interface (MOSI, MISO, SCK and SS)
- Supports slave select (SS) bit for each slave on the SPI bus
- Supports full-duplex operation
- Supports master and slave SPI modes
- Supports programmable clock phase and polarity
- Supports continuous transfer mode for automatic scanning of a peripheral
- Mature source IP has been re-engineered for full DAL-A compliance for airworthiness and design assurance for safety-critical programs, supporting and simplifying the compliance effort at the FPGA level.
- Encrypted source along with a complete certification data package (CDP) including all artifacts required for chip-level compliance.