Provides a bidirectional interface between a user IP core and the AXI4 interface standard. This version of the AXI Master Burst has been optimized for bus mastering operations consisting of burst transactions.
- Compatible with 32, 64, and 128-bit AXI4
- Parameterizable data width of Client IP Interface (IPIC) to 32, 64, or 128-bits
- Supports AXI4 read and write data burts of 16, 32, 64, 128, and 256 maximum data beats
- Transfer width is equal to the parameterized IPIC data width
- Automatic AXI4 4K byte address boundary crossing protection
- The User interface consists of a Legacy Command/Status interface and read and write LocalLink interfaces for the data transactions
- Mature source IP has been re-engineered for full DAL-A compliance for airworthiness and design assurance for safety-critical programs, supporting and simplifying the compliance effort at the FPGA level.
- Encrypted source along with a complete certification data package (CDP) including all artifacts required for chip-level compliance.