Concentrates multiple interrupt inputs from peripheral devices to a single interrupt output to the system processor.
- AXI interface is based on the AXI4-Lite specification
- Configurable number of (up to 32) interrupt inputs
- Single interrupt output
- Supports relocatable base address in MicroBlaze
- Easily cascaded to provide additional interrupt inputs
- Priority between interrupt requests is determined by vector position. The least significant bit (LSB, in this case bit 0) has the highest priority
- Interrupt Enable Register for selectively enabling individual interrupt inputs
- Master Enable Register for enabling interrupt request output
- Mature source IP has been re-engineered for full DAL-A compliance for airworthiness and design assurance for safety-critical programs, supporting and simplifying the compliance effort at the FPGA level.
- Encrypted source along with a complete certification data package (CDP) including all artifacts required for chip-level compliance.