Provides an easy way to implement ARINC 818 compliant interfaces in Xilinx® FPGAs. Avionics Digital Video Bus (ADVB) is a video interface and protocol standard developed for high bandwidth, low latency, uncompressed digital video transmission in avionics systems.
- Complete header/ancillary data recovery
- Embedded ancillary data with real time update
- Flexible video resolution/frame rates
- Low Latency
- Many pixel packing and input formats
- Progressive and interlaced video
- Receiver error and status detection
- Simple pixel bus transmitter interface
- Supports V5, V6 and S6
- Supports line synchronous transmission
- Supports link speeds up to 4.25 Gbps
- Mature source IP has been re-engineered for full DAL-A compliance for airworthiness and design assurance for safety-critical programs, supporting and simplifying the compliance effort at the FPGA level.
- Encrypted source along with a complete certification data package (CDP) including all artifacts required for chip-level compliance.