MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, N7, N5A)
DMA Controller with AHB IP
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DMA Controller with AHB IP verilog IP
- AHB Multi-Channel DMA Controller
- AHB Single Channel DMA Controller
- AMBA AHB 4 Channel DMA Controller
- AXI / AHB / APB - SPI Flash Memory Controller - Octal/Quad/Dual/Single SPI I/O - CPU access to Flash and optional Execute-in-Place (XIP), Boot, DMA
- AXI4 Multi-Channel DMA Controller
- Display Controller - LCD / OLED Panels (AHB Bus)