MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, N7, N5A)
DMA Controller
特色
- Multiple independent DMA channels
- Designed with synthesizable HDL for ASIC and PLD implementations in variou system environments
- Each channel programmable to two types of DMA transfers: memory-to-memory and memory-to-I/O data transfer.
- Supports both hardware initiated transfer and software initiated transfers.
- Programmable burst and single data transfer.
- Internal arbitration logic for multiple DMA channels.
- Interrupt generation on transfer completion.
- Optional DMA chaining for multiple DMA sessions.
查看 DMA Controller 详细介绍:
- 查看 DMA Controller 完整数据手册
- 联系 DMA Controller 供应商