Display Port 2-Lane Transmitter PHY

特色

• Fully compliant to DisplayPort specification version 1, revision 2a
• Includes 2 Lanes DisplayPort Transmitter
• Includes AUX Channel transceiver
• Supports data rate of 5.4/2.7/1.62 Gbps per lane
• Supports logic circuit for PMA-only PHY control (without protocol)
• Supports 10/12/25/27 MHz clock input source for High-speed multi-rate PLL
• Supports post-cursor 1 FFE for Main Link transmitter
• Supports 0.8 V TX output swing for Main Link transmitter
• Supports 0/3.5/6.0 dB Pre-emphasis for Main Link transmitter
• Supports 20-bit databus width of parallel interface
• Supports PLL-alive mode
• Supports built-in internal loopback mode for testing

优势

• Compact IP size and easy for integration
• Ultra low power consumption for DisplayPort v1.2
• Extensive testability including loopback mode

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