256x8 Bits OTP (One-Time Programmable) IP, TSMC 0.13um 1.5V/3.3V LP Process
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Display Port 1.2 Tx PHY & Controller IP (Silicon Proven in STMicro 28FDSOI)
Our Display Port is VESA DP1.1a, DP1.2 and eDP compliant with four main lanes and an auxiliary channel The DP transmitter acceptsDP1.1a HBR (2.7Gbps) and RBR (1.62Gbps) data rates; it can also support turbo mode (3.24Gbps) and HBRII (5.4Gbps) of DP1.2 standard. Signals are sampled from 1/2/4-lane double-wide DP stream data.
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Block Diagram of the Display Port 1.2 Tx PHY & Controller IP (Silicon Proven in STMicro 28FDSOI)
Display Port V1.2 Tx PHY IP IP
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