Display LVDS/MIPI D-PHY/sub-LVDS combo Transmitter 1.0G/2.5G/1.0Gbps 10-Lane

* The LVDS/Sub-LVDS/DPHY Combo TX converts parallel RGB data and 7/8/10 bits of CMOS parallel data into serial data streams. A phase-locked clock is transmitted in parallel with the data streams over a dedicated high-speed link. The polarity of differential signals for each data lane can be controlled. The CL12661M10T2DM2FIP transmitter is an ideal means to solve EMI and cable size issues associated with high-speed CMOS interface.
* This IP is expandable to 4, 5, 8, 10 or more lanes.
* Porting is also possible for processes other than the target process.
* We can provide the original LINK controller (soft macro) that can be used with this PHY.

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