65nm OTP Non Volatile Memory for Standard CMOS Logic Process
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Display Controller - LCD / OLED Panels (AHB-Lite Bus)
The Digital Blocks DB9000AHB-Lite TFT LCD Controller IP Core interfaces a microprocessor and frame buffer memory via the AMBA 3.0 AHB-Lite Bus V1.0 to a TFT LCD panel. In an FPGA, ASIC, or ASSP device, the microprocessor is typically an ARC, ARM, Intel, MIPS, OpenSPARC, PowerPC, or Tensilica processor and frame buffer memory is either on-chip SRAM memory or larger off-chip SRAM or SDRAM.
The DB9000AHB-Lite can connect directly to a multi-port memory controller with an AHB-Lite port interface.
The DB9000AHB-Lite can connect directly to a multi-port memory controller with an AHB-Lite port interface.
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Block Diagram of the Display Controller - LCD / OLED Panels (AHB-Lite Bus)
