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Digital PreDistortion IP
Developed for performance and portability, FlexDPD is readily configured for use on all major FPGA and ASIC targets. Systems4Silicon is independent of a device vendor, which facilitates design migration between FPGA vendors’ devices and from FPGA to ASIC.
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Block Diagram of the Digital PreDistortion IP
Video Demo of the Digital PreDistortion IP
An illustration of Systems4Silicon's Digital Pre-Distortion IP linearizing a 100W PA transmitting a APCO P25 Phase2 signal. The video starts with the PA partially linearized and then rapidly converging upon full linearization as the algorithm adapts.