Digital Delay Locked Loop (133MHz - 333MHz) - TSMC 90nm GT (CLN90GT)
查看 Digital Delay Locked Loop (133MHz - 333MHz) - TSMC 90nm GT (CLN90GT) 详细介绍:
- 查看 Digital Delay Locked Loop (133MHz - 333MHz) - TSMC 90nm GT (CLN90GT) 完整数据手册
- 联系 Digital Delay Locked Loop (133MHz - 333MHz) - TSMC 90nm GT (CLN90GT) 供应商
programmable PLL IP
- Fractional-N PLL Widely Programmable
- 40-450MHz Programmable Clock Generator PLL, SMIC0.13um
- Programmable CMOS PLL high-frequency divider
- Programmable CMOS PLL high-frequency divider
- TSMC GF Intel Samsung Fractional-N Frequency Synthesizer PLL
- TSMC GF Intel Samsung Integer-N Frequency Synthesizer PLL