MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, N7, N5A)
Differential Clock Receiver to CML - TSMC CLN2P
The Receiver macro is implemented in Analog Bits’ proprietary architecture that uses core and 1.2V IO devices operated at core voltage. In order to minimize noise coupling and maximize ease of use, the Receiver incorporates proprietary ESD structures, which is proven in several generations of processes.
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