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LPDDR5/4/4X PHY IP for TSMC N6
The DesignWare LPDDR5/4/4X PHY is Synopsys’ physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and systemin-package applications requiring high-performance LPDDR5, LPDDR4, and LPDDR4X SDRAM interfaces operating at up to 6400 Mbps. With flexible configuration options, the LPDDR5/4/4X PHY can be used in a variety of mobile applications supporting LPDDR5 and/or LPDDR4/4X SDRAMs, precisely targeting the specific power, performance, and area (PPA) requirements of these systems.
Optimized for high performance, low latency, low area, low power, and ease of integration, the LPDDR5/4/4X PHY is provided as hardened IP components (macrocells) to facilitate the following types of signals:
- Single-ended Command/Address (C/A) and Data (DQ) signals
- Differential signals (clock, data strobe, and WCK signals)
- CMOS logic-level based C/A signals
The macrocells include fully integrated IOs and are easily assembled into a variety of configurations supporting a wide range of SoC DRAM interface requirements. Supporting the GDSII-based PHY is the RTL-based PHY Utility Block (PUB) that features Synopsys’ unique firmware-based training capability. In addition to training the interface after boot-up, the PUB contains the configuration registers for the PHY, performs periodic delay line compensation against voltage and temperature drift, performs DRAM retraining, and facilitates ATE testing and interface diagnostics. The LPDDR5/4/4X PHY includes a DFI 5.0 interface to the memory controller and can be combined with the DesignWare LPDDR5/4/4X Controller for a complete DDR interface solution.
Optimized for high performance, low latency, low area, low power, and ease of integration, the LPDDR5/4/4X PHY is provided as hardened IP components (macrocells) to facilitate the following types of signals:
- Single-ended Command/Address (C/A) and Data (DQ) signals
- Differential signals (clock, data strobe, and WCK signals)
- CMOS logic-level based C/A signals
The macrocells include fully integrated IOs and are easily assembled into a variety of configurations supporting a wide range of SoC DRAM interface requirements. Supporting the GDSII-based PHY is the RTL-based PHY Utility Block (PUB) that features Synopsys’ unique firmware-based training capability. In addition to training the interface after boot-up, the PUB contains the configuration registers for the PHY, performs periodic delay line compensation against voltage and temperature drift, performs DRAM retraining, and facilitates ATE testing and interface diagnostics. The LPDDR5/4/4X PHY includes a DFI 5.0 interface to the memory controller and can be combined with the DesignWare LPDDR5/4/4X Controller for a complete DDR interface solution.
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Video Demo of the DesignWare LPDDR5/4/4X PHY IP for TSMC N6
SDRAMs such as DDR, LPDDR, and HBM offer unique advantages for automotive, artificial intelligence (AI), cloud, and mobile applications. However, the selected memory solution impacts the performance, power, and area requirements of SoCs, making it important to choose the right memory technology and interface IP for the target design. Meet your specific design targets by using Synopsys’ high-performance, silicon-proven DDR memory interface IP solutions compliant with the latest JEDEC standards.