PowerVR Neural Network Accelerator - The perfect choice for cost-sensitive devices
You are here:
DDR5/4 Controller IP with a CHI Interface
DesignWare® DDR5/4 Controller is a next-generation memory controller optimized for latency, bandwidth, and area., supporting JEDEC standard DDR5 and DDR4 SDRAMs and DIMMs The highly configurable controller meets or exceeds the design requirements of a wide range of applications from data center to consumer.
The DesignWare DDR5/4 Controller connects to the DesignWare DDR5/4 PHY or other PHYs via the DFI 5.0 interface to create a complete memory interface solution.
The controller includes software configuration registers, which are accessed through an AMBA 3.0 APB interface. The DDR controller block includes advanced command scheduler, memory protocol handler, optional ECC (Error-correcting code), and dual-channel support, as well as the DFI interface to the PHY.
The DesignWare DDR5/4 Controller connects to the DesignWare DDR5/4 PHY or other PHYs via the DFI 5.0 interface to create a complete memory interface solution.
The controller includes software configuration registers, which are accessed through an AMBA 3.0 APB interface. The DDR controller block includes advanced command scheduler, memory protocol handler, optional ECC (Error-correcting code), and dual-channel support, as well as the DFI interface to the PHY.
查看 DesignWare DDR5/4 Controller IP with a CHI Interface 详细介绍：
- 查看 DesignWare DDR5/4 Controller IP with a CHI Interface 完整数据手册
- 联系 DesignWare DDR5/4 Controller IP with a CHI Interface 供应商
DDR5/4 Controller IP
- DDR5/4 PHY in TSMC (16nm, 7nm)
- DesignWare DDR5/4 Controller IP with Advanced Features Package
- DDR and LPDDR 4/3/2 controllers for low power and high Reliability, Availability and Serviceability (RAS) targeting automotive
- Synopsys DDR5/4 PHY IP on SS7HPP
- DesignWare® DDR5/4 PHY IP for TSMC 12FFC
- DesignWare® DDR5/4 PHY IP for TSMC 16FFC