7 µW always on Audio feature extraction with filter banks on TSMC 22nm uLL
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DES and Triple DES (TDES or 3DES) encryption and decryption coprocessor
The Triple DES Coprocessor is a Data Encryption Standard (FIPS 46-3) peripheral computing DES and Triple DES (TDES and 3DES) encryption and decryption through a highly-optimized secure architecture. Based on 2.5 kgates, the Triple DES Coprocessor computes DES and 3DES in 16 and 48 cycles respectively.
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Triple IP
- Secure-IC's Securyzr™ Tunable DES - Triple DES (ECB, CBC, CTR) accelerator - optional SCA protection
- Triple DES core
- DES and Triple DES data encryption / decryption
- 10bit triple video DAC (Vcc/Vdd=3.3/1.8V, DNL:+/- 1/2LSB,INL:+/- 1/2LSB)
- 10/100/1000 Ethernet (Triple Speed)
- Triple Video DAC 10-Bits, 240Mhz