DDR4 PHY

The DDR4 multiPHY is a complete mixed-signal IP solution designed to provide LPDDR3/LPDDR2/DDR3/DDR3U/DDR3L/DDR4 SDRAM connectivity in a System-On-a-Chip (SOC) design targeted to a specific fabrication process. The DDR4 multiPHY supports a range of SDRAM speeds, from DDR3-400 through DDR4-2400. Targeted toward supporting, x8 and x16 SDRAM components, DDR4 multiPHY supports interfaces of varying widths, from a minimum of 8 bits wide, in 8-bit increments. Delivered to customers as hardened IP components —Address/Command (AC), Data (DAT), PLL, and SSTL I/O Library —implementations of the DDR4 multiPHY are compatible with JEDEC DDR SDRAMs, helping ensure customer success.

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