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DDR4 multiPHY in Samsung (14nm)

Synopsys DesignWare® DDR4 multiPHY IP cores are mixed-signal PHY IP cores that supply the complete physical interface to JEDEC standard DDR4, DDR3, LPDDR2, and LPDDR3 SDRAM memories. The DDR4 multiPHY IP supports DDR4 SDRAM speeds from DDR4-1333 through DDR4-2667, DDR3 SDRAM speeds from DDR3-666 to DDR3-2133, LPDDR2 SDRAMs from 0 to 1066 Mbps and LPDDR3 SDRAMs from 0 to 2133 Mbps. The DDR4 multiPHY IP cores are compiled into a hard macro that is optimized for specific foundry nodes. Each DDR4 multiPHY is constructed from the following libraries of components: the application specific SSTL I/O library, a single address/command macro block, multiple byte wide data macro blocks instantiated as many times as required to accommodate the memory channel width, and separate PLL macrocells that directly abut to the address/command macro block and data macro blocks.

A key component of the DesignWare DDR4 multiPHY is the extensive in-system data training/calibration capability used to maximize the overall timing budget and improve system reliability. The DesignWare DDR4 multiPHY contains calibration circuits for read data eye training (optimizes and maintains the optimal DQS offset into the center of the read data eye), write data eye training (optimizes and maintains the optimal DQS offset into the center of the write data eye), per-bit deskew training (minimizes bit to bit timing skew for reads and writes independently), DDR3 write leveling, and DDR3 read leveling. The DDR4 multiPHY also supports per-bit deskew calibration of the address/command bus for LPDDR3 SDRAMs and VREF level training for DDR4 SDRAMs.

特色

Low latency, small area, low power
Compatible with JEDEC standard DDR4 up to 2667 Mbps
Compatible with JEDEC standard DDR3 SDRAMs up to 2133 Mbps – Supports DDR3L (1.35V DDR3) up to 1866 Mbps – Supports DDR3U (1.25V DDR3) up to 1600 Mbps
Compatible with JEDEC standard LPDDR2 SDRAMs up to 1066 Mbps
Compatible with JEDEC standard LPDDR3 SDRAMs up to 2133 Mbps
DFI 3.1 compliant interface to the memory controller – 1:1 and 1:2 clock modes supported – 1:1 or 1:2 clock mode can be selected via software at boot time
Support for 4-bit, 8-bit, 16-bit and 32-bit wide SDRAMs – 2-channel (64-bit) LPDDR2 and LPDDR3 SDRAM supported
Support for SDRAM components soldered directly to PCB
Support for DDR4 and DDR3 UDIMMs and RDIMMs
Data path width scales in 8-bit increments from 8 bits to 72 bits
Support for partially populated interfaces

优势

Supports JEDEC standard DDR4, DDR3, DDR3L (1.35V DDR3) , DDR3U (1.25V DDR3), LPDDR2, and LPDDR3 SDRAMs
High-performance DDR PHY supporting data rates from 0 to 2667 Mbps
Per-bit deskew for both read and write data paths
Per-bit deskew for address/ command bus when used with LPDDR3 SDRAMs
Designed for rapid integration with Synopsys Universal Protocol or Memory Controllers for a complete DDR interface solution
Includes applicationspecific DDR I/Os including programmable drive strength and On-Die Termination (ODT)
DFI 3.1 compliant controller interface

可交付内容

Executable .run installation file which includes GDSII, LEF Files, LVS Netlists, .lib/.db Timing Models, Verilog Model, DRC/LVS Log Files, I/O IBIS Model, I/O HSPICE Netlist, Parameterized Verilog top-level PHY netlist files, Sample Verification Environment, PHY Data Book, Physical Implementation Guide, App Notes, Verification Guide, Installation Guide, Implementation Checklist
The PHY Utility Block includes Verilog Code, Synthesis/STA constraints and scripts, Sample Verification Environment, Data Book
DDR PHY Compiler

应用

Data centers (networking and storage)
Digital home
Mobile multimedia
Wireless connectivity
Digital office

Video Demo of the DDR4 multiPHY in Samsung (14nm)

SDRAMs such as DDR, LPDDR, and HBM offer unique advantages for automotive, artificial intelligence (AI), cloud, and mobile applications. However, the selected memory solution impacts the performance, power, and area requirements of SoCs, making it important to choose the right memory technology and interface IP for the target design. Meet your specific design targets by using Synopsys’ high-performance, silicon-proven DDR memory interface IP solutions compliant with the latest JEDEC standards.