MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, N7, N5A)
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DDR3/LPDDR23 PHY - 55LL
B55LLDDRPHY-D3LP23 IP is compliant to JESD79-3F(DDR3), JESD209-2F(LPDDR2), JESD209-3B(LPDDR3),DFI3.1 specification and delivers an unbeatable combination of DDR speed and low power operation. With DSCL and DABC technology, B55LLDDRPHY-D3LP23 IP can automatically compensate chip/package/board/memory PVT variation and bit-bit skew. B55LLDDRPHY-D3LP23 delivers the highest DDR performance, the smallest area and the shortest bring up time.
It is easy to integrate B55LLDDRPHY-D3LP23 with BDDRCTL-D3LP23 controller IP or other third party DDR controller through the AHB/APB register interface and DFI3.1 interface. Technique support will be provided to help the customer for integration/validation.
It is easy to integrate B55LLDDRPHY-D3LP23 with BDDRCTL-D3LP23 controller IP or other third party DDR controller through the AHB/APB register interface and DFI3.1 interface. Technique support will be provided to help the customer for integration/validation.
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