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DDR3/2 PHY
The DDR3/2 PHY is a complete mixed-signal IP solution designed to provide DDR 3/2 SDRAM connectivity in a System-On-a-Chip (SOC) design targeted to a specific fabrication process. The DDR3/2 PHY supports a range of DDR3 SDRAM speeds, from DDR3-667 through DDR3-1600, with backward compatibility provided for DDR2-667 through DDR2-1066 devices. Targeted toward supporting x8 and x16 DDR3 SDRAM components, DDR3/2 PHY supports interfaces of varying widths, from a minimum of 8 bits wide, in 8-bit increments. Delivered to customers as hardened IP components— Address/Command, DATX8, and SSTL I/O Library—implementations of the DDR3/2 PHY are compatible with JEDEC DDR2 and DDR3 SDRAMs, helping ensure customer success.
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DDR3/2 IP
- LPDDR3/2/DDR3/3L Combo PHY & Controller
- LPDDR3/2/DDR3/3L/2 Combo PHY & Controller
- DDR3/3L/2/LPDDR3/2 Combo PHY & Controller
- DDR3/3L/2 Combo PHY & Controller
- DDR3/2 COMBO PHY CMD/ADDR BLOCK for 2 layer 8 bits DDR3 PCB ; UMC 40LP/RVT LowK Logic Process with 2.5V device
- DDR3/2 COMBO PHY DATA BLOCK for 2 layer 8 bits DDR3 PCB ; UMC 40LP/RVT LowK Logic Process with 2.5V device