ARC-V RHX-105 dual-issue, 32-bit RISC-V processor for real-time applications (multi-core)
DDR SDRAM Controller
Whether you use the IP Toolbench in SOPC Builder or the Quartus®II software, it generates an example design, instantiates a phase-locked loop (PLL), an example driver, and your DDR/DDR2 SDRAM Controller custom variation. The example design is a fully-functional example design that can be simulated, synthesized, and used in hardware. The example driver is a self-test module that issues read and write commands to the controller and checks the read data to produce the pass/fail and test complete signals.
You can replace the DDR/DDR2 SDRAM controller encrypted control logic in the example instance with your own custom logic, which allows you to use the Altera® clear-text data path with your own control logic.
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