MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, N7, N5A)
DDR SDRAM Controller
特色
- Supports industry standard Double Data Rate (DDR) SDRAM.
- Designed for ASIC and FPGA implementations in various system environments.
- Programmable memory size and data width.
- Supports industrial standard 64Mbit, 128Mbit and 256Mbit DDR SDRAMs.
- Provides user data at twice the data width compared to DDR SDRAM data.
- Supports burst size of 2 to 8 words.
- Supports zero wait state burst data transfer to maximize data bandwidth.
- Programmable SDRAM access timing parameters.
- Automatic refresh generation with programmable refresh intervals.
- Optional Error Correction Code (ECC).
- Multiple external DDR SDRAM partitions.
- Fully synchronized design based on user supplied clock.
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