DDR multi PHY

The DDR multiPHYs are mixed-signal PHY IP cores that supply the complete physical interface to JEDEC standard DDR2, DDR3, LPDDR2, LPDDR3 SDRAM memories up to 1066 Mbps data rates and Mobile DDR (also referred to as mDDR and LPDDR) SDRAM memories up to 400 Mbps data rates. This particular PHY supports switching between DDR2 and DDR3 memories once a chip is in production. This “Lite” PHY does not go up to the full 1600 Mbps data rate targeted for DDR3. Instead, this is an area and feature optimized DDR2/DDR3 PHY for customers that want to go to market with DDR2 interfaces up to 1066 Mbps and also want an insurance policy against equivalent DDR3 devices becoming cheaper while their chip remains in the market. As part of the optimization of this PHY, a small number of the new features for DDR3, such as write leveling, are not supported as they are not supported by DDR2 SDRAMs.

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