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DDR, Digital Configurable Delay line module
DDR module configure and set the number of delay elements in half a cycle of the input clock.
Configuration resolution is 4Bits.
The DDR module set , position and align the strobe Tap at configurable fractional input clock cycle after the clock edge.
Configuration resolution is 4Bits.
The DDR module set , position and align the strobe Tap at configurable fractional input clock cycle after the clock edge.
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