MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, N7, N5A)
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DC-DC IP, Input: 3.3V, Output: 5V/50mA, UMC 0.153um MS process
Pulse Width Modulation, boosting voltage from 3.3V to 5V/50mA driving capability, Ivcca=140uA@Idrive=0, UMC 0.153um Logic/Mixed-Mode process.
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