USB 3.2 Gen2/Gen1 PHY IP in TSMC(5nm, 6nm, 7nm,12nm/16nm, 22nm, 28nm, 40nm, 55nm)
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DC-DC IP, Input: 0.95V - 1.5V, Output: 3V/100mA, UMC 0.11um HS/AE process
0.95V~1.5V to 3.0V DC-DC converter with 100mA driving capability, UMC 0.11um HS/AE (AL Advanced Enhancement) Logic process.
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