1-56/112G Multi-protocol Serdes (Interlaken, JESD204, CPRI, Ethernet, OIF/CEI)
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D-MAC-10/100
Our innovative solution is a hardware implementation of media access control protocol defined by the IEEE standard. DMAC in cooperation with external PHY device enables network functionality in design. It is capable to transmit and receive Ethernet frames to and from the network. Half and full duplex modes are supported, as well 10 and 100 Mbit/s speed. The Core is able to work with wide range of processors: 8, 16 and 32 bit data bus, either little or big endian byte order format. The DMAC provides static configuration of PHY IC. Please remember that our design is technology independent and thus can be implemented in variety of process technologies. This Core strictly conforms to IEEE 802.3 standard.
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Block Diagram of the D-MAC-10/100

Ethernet IP
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- 1-56/112G Multi-protocol Serdes (Interlaken, JESD204, CPRI, Ethernet, OIF/CEI)
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