MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, N7, N5A)
D/A Converter IP, 10 bits, 150Msps, UMC 40nm LP process
查看 D/A Converter IP, 10 bits, 150Msps, UMC 40nm LP process 详细介绍:
- 查看 D/A Converter IP, 10 bits, 150Msps, UMC 40nm LP process 完整数据手册
- 联系 D/A Converter IP, 10 bits, 150Msps, UMC 40nm LP process 供应商
ADC/DAC IP
- 12bit 5Gsps silicon proven High performance Current Steering DAC IP Core
- Audio codec with capacitor-less 106 dB dynamic range ADC and 120 dB SNR DAC with low latency
- 12-bit 12-Gsps Transceiver (ADC/DAC/PLL)
- 8-bit 48-Gsps Transceiver (ADC/DAC/DLL)
- UCIe based 12-bit 12-Gsps Transceiver (ADC/DAC/PLL/UCIe)
- UCIe based 8-bit 48-Gsps Transceiver (ADC/DAC/PLL/UCIe)