The V-Trans VT18DCXO crystal oscillator cell provides a low phase-noise output, with a low frequency variation over temperature.
Oscillation frequency can be digitally adjusted ( +/- 100ppm)
In power-down mode, the oscillator is bypassed. An external clock signal can be applied to “xin” pin.
Internal current reference generator allows the cell to be used as a stand-alone.
If a more accurate current reference is desired, for better control or extended range of oscillation frequency over PVT corners, the user can apply an external current reference. (25uA typical).
A such reference current can be provided by V-Trans Irefgen (resistor-less design +/-5%) or Refgen (with external reference resistor +/- 1%) libraries or any other third party IP.
- 10 to 30Mhz crystal
- Clock synchronization with 5bits frequency adjustment ( ±100ppm)
- Phase noise [contact us]dBc/Hz at 1kHz offset [contact us]dBc/Hz at 10kHz offset
- Clock input for bypass mode
- 3.3V/1.8V ±10% supply voltage, -40/+125°C
- 1P6M layout structure based on 0.18um 1P6M 3.3V/1.8V generic logic process.
- Core cell area (I/O included) : [contact us]
- Near 50% duty cycle output.
- Antenna diodes on each digital input.
- Built in I/Os with ESD protection.
- Silicon proven.
- low cost
- easy to integrate
- full support
- Design Kit includes:
- LEF view and abstract gdsII
- Verilog HDL behavioral model
- Liberty (.lib) timing constraints for typical, worse and best corner case
- Full Datasheet /Application Note with integration guidelines document
- Silicon characterization report when available
- Tapeout kit includes the design kit plus plysical view:
- LVS netlist and report
- DRC/ERC/ESD/ANT report