Comcores Physical Coding Sublayer (PCS) IP core for CPRI 7.0 is a silicon agnostic implementation of the PCS layer described in IEEE Ethernet standard IEEE 802.3 - 2012 and default conﬁgured to meet the requirements of CPRI 7.0. The PCS IP-core enables transmission and reception of data via SerDes interfaces. It is designed to enable easy upgrade of CPRI 5.0 or older version to run with the highest line-speeds.
The core can be dynamically conﬁgured to enable either 8B/10B or 64B/66B encoding/decoding and includes full RS-FEC functionality
To ensure easy integration build-in test capabilities are provided in the core.