NVM OTP NeoBit in UMC (180nm, 160nm, 130nm, 110nm, 80nm, 55nm)
Cortex M1
CoreCortexM1 processor runs a subset of the Thumb-2 instruction set (ARMv6-M) that includes all base 16-bit Thumb instructions and a few Thumb-2 32-bit instructions (BL, MRS, MSR, ISB, DSB, and DMB). This enables writing very tight and efficient processor code, which is ideal for the limited memory typically found in deeply-embedded applications.
Cortex M1 is licensed under the terms of ARM Cortex-M1 End User License Agreement (EULA). Users are required to fill EULA available at https://www.microsemi.com/form/91-coreip-cortex-m1 to obtain the core.
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