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Core Powered Frac-N SSCG PLL - TSMC CLN3A
Analog Bits’ Core Powered Fractional-N / Spread Spectrum PLL is an easy to integrate macro, requiring no analog power supply, and can be placed anywhere on a chip.
This Fractional-N / Spread Spectrum PLL addresses power sensitive designs required for IOT, mobile and other low power applications needing non-integer clock multiplication, programmable clock synthesis, and clock tracking for fine tuning on-the-fly. The PLLs are designed for digital logic processes and use robust design techniques to work in noisy SoC environments, such as high speed communication to low power consumer to memory interfaces.
The programmable Fractional-N divider allows the PLL to lock to an incoming clock source and produce an output clock with a non-integer multiplication factor. The generated clock can be locked to the input source yet adjusted to a fine-degree of precision, and may be adjusted on-the-fly to maintain a relatively drifting local clock need. The updatable programmable fractional feedback divider is provided for this purpose. “On the fly” capability means the frequency transition and re-obtaining lock process for small frequency adjustment is glitch free and contains limited frequency over/undershoot.
Furthermore, it is a requirement by the FCC and equivalent international bodies that electronic devices including game-consoles, PCs, and high speed compute servers, limit Electromagnetic Interference (EMI) when they operate. The Spread Spectrum function of the PLL is capable of generating precise clock spreads (using a triangular modulation profile) that help reduce EMI. Programmable options allow the user to control the degree of spread in fine steps of modulation frequency and depth.
The PLL macro is implemented in Analog Bits’ proprietary architecture that uses core and thick-oxide (1.2V and 1.2V-OD-1.5V) devices operated on a core voltage level power supply.
This Fractional-N / Spread Spectrum PLL addresses power sensitive designs required for IOT, mobile and other low power applications needing non-integer clock multiplication, programmable clock synthesis, and clock tracking for fine tuning on-the-fly. The PLLs are designed for digital logic processes and use robust design techniques to work in noisy SoC environments, such as high speed communication to low power consumer to memory interfaces.
The programmable Fractional-N divider allows the PLL to lock to an incoming clock source and produce an output clock with a non-integer multiplication factor. The generated clock can be locked to the input source yet adjusted to a fine-degree of precision, and may be adjusted on-the-fly to maintain a relatively drifting local clock need. The updatable programmable fractional feedback divider is provided for this purpose. “On the fly” capability means the frequency transition and re-obtaining lock process for small frequency adjustment is glitch free and contains limited frequency over/undershoot.
Furthermore, it is a requirement by the FCC and equivalent international bodies that electronic devices including game-consoles, PCs, and high speed compute servers, limit Electromagnetic Interference (EMI) when they operate. The Spread Spectrum function of the PLL is capable of generating precise clock spreads (using a triangular modulation profile) that help reduce EMI. Programmable options allow the user to control the degree of spread in fine steps of modulation frequency and depth.
The PLL macro is implemented in Analog Bits’ proprietary architecture that uses core and thick-oxide (1.2V and 1.2V-OD-1.5V) devices operated on a core voltage level power supply.
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