The BSIGF65LP-PLL is a Low Power wide-range, high-bandwidth, low-jitter Phase Locked-Loop, its 6 output counters can be configured post production
- Support spread-spectrum reference clock tracking
- Triangular Modulation frequency: less than 75KHz
- Down spread or center spread: less than 2.5% (p-p)
- Support internal feedback (internal compensation) and external feedback (external compensation).
- 6 phase output clock configuration (through metal configuration). 6 phase output clock is targeted for oversampling application, eg. soft CDR.
- Programmable reference clock divider, feedback clock divider, output clock divider
- PLL output counter
- Total of 6 output counters.
- Each counter can be enabled/disabled independently. When not in use, they can be disabled to save power.
- Each PLL output is able to phase shift independently.
- Bypass mux for all outputs (mux’ed ref/test clock to output clock)
- Selectable output inversion
- AC Scan requirement: programmable no. of at-speed clock pulse (1, 2 pulses or continuous) and scan capture control input for each output counter.
- All output counters will be synchronized upon proper startup
- Support output counter cascading.
- Support PLL cascading
- Hard-IP - physical layout (GDSII) for GlobalFoundries 65nm LPE process
- LVS/CDL netlists
- Verilog simulation models (Tetramax and ATPG compatible)
- Synopsys Liberty files
- Physical LEF (Cadence)
- Specification, integration, and usage documentation