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PCI Express 3.0, 2.0, 1.1 Controller IP Core with AMBA AXI User Interface
The PCI Express 3.0, 2.0, 1.1 Controller IP Core with AXI interface is a high performance, highly-configurable PCI Express® interface IP compliant to the PCI Express® rev.3.0 specification. The PCI Express 3.0, 2.0, 1.1 Controller inherits the leading architecture and reliability of previous generations of PCI Express interface IP and features an AXI user interface with built-in DMA, compliant to the AMBA AXI3 and AXI4 specifications.
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Block Diagram of the PCIe 3.1 / 3.0根端口，端点，双模，Controller IP内核， 内置DMA和可配置AMBA AXI互连
PCI Express Controller IP
- Complete PCIe 4.0 Soft IP supporting endpoint, root port, switch, bridge and advanced features such as SR-IOV, multi-function, data protection (ECC, ECRC), ATS, TPH, AER and more
- Configurable PCI Express 2.1 Supporting Root Port, Endpoint, Dual-mode Configurations, with Built-in DMA and Configurable AMBA AXI Interconnect
- Controller IP for PCIe 2.1 as well as with the PHY Interface for PCI Express (PIPE) specification and the AMBA® AXI™ Protocol Specification
- Configurable PCI Express 1.1 Supporting Root Port, Endpoint, Dual-mode Configurations, with Built-in DMA and Configurable AMBA AXI Interconnect
- Controller IP for PCIe 1.1 as well as with the PHY Interface for PCI Express (PIPE) specification and the AMBA® AXI™ Protocol Specification
- Gen5 PCIe Hybrid Controller with SR-IOV and ARI Support