PCI Express 3.0, 2.0, 1.1 Controller IP Core - Configurable
The PCI Express 3.0, 2.0, 1.1 Controller IP Core is a PCI Express endpoint, root port, and switch IP compliant to the PCI Express rev.3.0 specification
Complies with the PCI Express® Base 3.0 Draft Specification, rev.3.0
Supports Endpoint, Root-Port, Dual-Role, Switch configurations
Supports x16, x8, x4, x2, x1 at Gen3, Gen2, Gen1 speeds
Implements one Virtual Channel
Maximum payload size of up to 4KB.
符合PCI Express 3.1 / 3.0和PIPE（16位和32位）规范
符合PCI-SIGSingle-Root I / O Virtualization （SR-IOV）规范
Enhanced support of SR-IOV (single root I/O virtualization) within their XpressRICH3 PCI Express Gen3 IP solution, enabling customers to deploy virtualized applications more quickly and efficiently directly from within the PCI Express interface. The PLDA soft IP solution with SR-IOV capability is available for ASIC and FPGA and has been extensively tested on PLDA leading edge FPGA boards. The solution provides up to Gen3 x16 support, making PLDA the PCIe Gen3 IP of choice for leading ASIC and FPGA designs. - See more at: https://www.plda.com/plda-announces-enhanced-sr-iov-support-their-xpressrich3-pci-express-gen3-ip-solution-providing-512
Creating an intrinsic end-to-end data protection capability that is transparent to the end users and a deliver a minimum impact on throughput and latency
Providing a lower total cost of ownership and smaller carbon footprint
Reducing production costs and time to market through interface standardization
Block Diagram of the PCIe 3.1 / 3.0根端口，端点，双模，具有Native用户界面 的交换机端口Controller IP核
Video Demo of the PCIe 3.1 / 3.0根端口，端点，双模，具有Native用户界面 的交换机端口Controller IP核
In this video, we talk about the PLDA XpressRICH IP wizard which has been designed to enable PCIe designers to easily configure their PCIe controller as required for their application.